Projection of organic substrate warp is critical to cost effective development and production of an electronic module (microelectronic package). Current warp prediction (estimation) methodologies rely on significant approximations of the circuit structure of an organic chip carrier (substrate). These current prediction methods lead to a warp prediction that is often inaccurate, and thus not very useful. Ultimately, these inaccuracies result in organic chip carriers that are higher in cost and/or less reliable than desired. This can occur, for example, when an integrated circuit (IC) chip cannot be joined to the chip site due to poor chip site co-planarity. In other words, a flat chip cannot be joined to a non-flat substrate because interconnections may be misaligned causing electrical open-circuits.
Another manifestation of poor warp prediction is where, due at least in part to warp of the chip carrier, some inputs/outputs (I/O) of the chip cannot be connected to the organic chip carrier I/O where other chip I/O is able to be in a correct proximity to be joined. This may cause a high rework rate in manufacturing, thereby causing costs to increase. If this defect is not detected during in-line electrical testing, the reliability of the organic chip carrier may be compromised.
A silicon die with high density I/O requires an organic substrate to facilitate integration on a system board. A substrate usually consists of a core at the center and multiple layers of metal interconnects on both sides of the core. A substrate facilitates the formation of electrical links to the system board. The substrate also protects the die and modularizes the product development effort while simplifying the subsequent integration steps involved in the manufacturing of a larger computer or a consumer electronic product. The present trend in substrate technology is to transition from ceramic-based substrates to organic material-based systems. An organic polymer-based electronic substrate is a cost-effective means to fan out the I/O and power connections from a high density silicon die.
Organic substrates typically have a core about 400-800 microns (μm) thick, made of glass-fiber reinforced organic or resin material. In order to reduce cost, the core is eliminated in some substrates (e.g., coreless substrate). Metal interconnects are progressively built, layer-by-layer, on a top and bottom of the core by a series of process steps. These steps typically involve electroless-plating, electroplating, etching, polishing, placement of dielectric resin, high temperature pressing of resin, etc. Each circuit interconnect layer or a power or ground plane is separated by a sheet of photosensitive resin. Laser drilling of the resin and an electroplating process are used to fabricate vias that help connect various conductive (metal) layers. Multi-stack vias are often used to link conductive layers that are further apart within the build layers of a substrate.
The build layers between the IC die and the core are generally referred to as “FC” front circuit) layers, and the layers on the opposite side of the core are generally referred to as “BC” (bottom circuit) layers. Since each metal layer is designed to optimize electrical performance, the mechanical characteristics of each metal layer is not precisely controlled. The FC layers generally have a dense interconnect structure made of metal lines, typically etched from a layer of copper deposited by means of a plating process. The BC layers, on the other hand, tend to have a continuous sheet of copper with distributed holes for vias to pass through. Such a configuration inevitably leads to a substrate with asymmetric thermo-mechanical properties when viewed with respect to a center plane of the core.
A substrate design with asymmetric thermo-mechanical properties produces a warp when it is constructed at high temperature and cooled down to room temperature. Work by L. Valdevit et al., Microelectronics Reliability 48 (2008) p. 245-260, published by Elsevier Ltd., the disclosure of which is incorporated herein by reference, provides a thermo-mechanical model that accounts for heterogeneity and anisotropy of an organic chip board design file representative of an organic chip carrier (substrate). In this model, standard laminate plate theory is considered in the calculation of Young's moduli, Poisson's ratio and coefficients of thermal expansion of an organic chip carrier to predict warp. Preliminary warp prediction of a flip-chip (C4) organic chip carrier is presented.
Electronic manufacturing and assembly operations incorporating a substrate typically require the substrate to exhibit a warp that is within a minimum acceptable range. For example, for a substrate with 55×55 millimeter (mm) dimensions in an x-y plane, a warp of up to about 100 μm is typically considered acceptable. As the number of buildup layers and core thicknesses are changed, the warp levels can change according to their interaction with one another. The yield of substrates can be undesirably reduced if thermomechanical parametric symmetry (e.g., coefficient of thermal expansion (CTE), modulus, etc.) is not maintained within corresponding limits.